Cavium introduces Octeon III multi-core processor

Networking chipmaker Cavium has introduced its Octeon III MIPS64 family of 1-48 core multi-core processors that deliver over 100Gbps of application performance per chip, and allow for linear scaling across multiple chips in a fully coherent fashion. The 2.5GHz Octeon III processors provide compute power of any standards-based communications processor chip, at 120GHz of 64-bit compute processing per chip. Octeon III delivers up to four times higher application performance and it is the SoC to integrate high-performance search processing used from Cavium's Neuron Search processors along with fifth generation DPI Acceleration. Cavium's cnMIPS64 III cores offer up to 120GHz of compute, up to 48 superscalar MIPS64 cores, operating at up to 2.5GHz. Cavium's 3G custom cnMIPS 'Real Cores' include core-architecture enhancements, larger caches and short, efficient pipelines. New 20 plus Tbps HyperConnect provides access to an associative L2 cache running at full core-frequency. Low latency coherency architecture enables multi socket designs. This enables multiple Octeon III chips to appear as a single logical high-performance processor with up to 384 cores, providing up to 960GHz compute, up to 800 plus Gbps of application performance and up to 2 TBs of memory capacity at a lower latency. Octeon III is accompanied by Cavium's SDK, hardened APIs and software stacks for a variety of networking, security and storage applications. Octeon III is supported by Cavium's ecosystem of over 100 PACE partners who deliver optimised Octeon multi-core services across OS, development tools, applications, middleware and a range of hardware platforms. Hardware design collateral is available. First 28nm Octeon III silicon is expected to sample in the second half of this year.