Inphi launches 100 GbE CMOS PHY products

Analogue semiconductor systems provider Inphi has launched low power 100 GbE CMOS PHY products that support the IEEE 802.3ba standard and target enhanced 100G line cards. Based on Inphi's iPHY architecture, the IN112510 100GbE CMOS Gearbox (GB) and IN012525 100GbE CMOS Clock Data Recovery (CDR) chipsets will enhance time-to-market for high aggregate bandwidth systems while containing costs of enhanced 100GbE line cards targeted for data centre and enterprise networks. Inphi's iPHY CMOS PHY services will enable service providers to upgrade to 100GbE networks while retaining a lower carbon footprint. By integrating multiple channels along with transmit and receive functions on a single IC, Inphi is able to double the levels of integration available from existing 100GbE PHY and CDR offerings. The iPHY IN112510 is a single-chip, low-power PHY for 10:4 gearbox applications for 100GbE and OTU4 high-density 100 Gbps line cards with 25-28 Gbps electrical interfaces. iPHY IN112510 supports 100G BASE-LR4/ER4 and OTU4 28Gbps operation for OTL4.4, can be optimised for low-latency to allow use in ultra low latency applications. The service also features programmable transmit and adaptive receive equalisation on all SerDes interfaces with granularity and control which allow performance to surpass IEEE CAUI, CEI-11G SR and CEI-28G VSR specifications iPHY IN112510 features package design that allows denser line cards, optimisations for enhanced CFP2-based line card designs and single-chip low power service that allows enhanced optimised CFP modules. The iPHY IN012525 is a low-power CDR for 100GbE and OTU4 enhanced 100G modules. This CDR supports 100G BASE-LR4/ER4 and OTU4 28Gbps operation, programmable transmit and adaptive receive equalisation on all SerDes interfaces with fine granularity and control which allow performance to surpass CEI-28G VSR specifications. The product can be optimisated for enhanced CFP2 modules. Both iPHY IN112510 and iPHY IN012525 can eye-scan and monitor on all SerDes receiver interfaces for link margin and stress testing in a lab or production test environment. The self-test modes feature allows diagnostic monitoring of channel and system parameters.